PIPE5TRE

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Interpret as PIPE5TRE

TRENB=0, TRCLR=0

Pipe 5 Transaction Counter Enable Register

Reserved	These bits are read as 00000000. The write value should be 00000000.
TRCLR	Transaction Counter Clear 0 (0): Invalid 1 (1): The current counter value is cleared.
TRENB	Transaction Counter Enable 0 (0): Transaction counter is disabled. 1 (1): Transaction counter is enabled.
Reserved	These bits are read as 000000. The write value should be 000000.

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